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Research
Agenda
Year:
2005-2006
Students:
Jonathan Torian
Ronnie Hudson
Mentor:
Pranav Anbalagan
Research Area:
Wire length prediction using statistical
methods
Proposed Research:
This project aims to develop an application that will
be able to predict wire sizes between gates given a gate layout. In order
to complete this, we will learn the basics of data mining using
classification trees. We will use classification and regression trees for
statistical analysis. After understanding the statistical portion, we will
learn the basics of chip design flow and placement in particular. Following
this, we will have a basic review of wire length prediction concepts.
Finally, we will apply statistical concepts to the problem of wire length
prediction and hence, will develop a wire length prediction model. If time
permits, we will develop models for estimating area, power, and performance
based on prediction model developed.
Timeline:
November:
 | Read information to understand classification trees
and data mining. |
| Find out if there are any tools available to perform
the CRT (Classification and Regression Tree) algorithm |
| Target – Know basics of classification trees,
classification and regression tree models, placement of gates |
December:
| Target – Decide on what method to use to develop the
classification tree (use a tool that is current available or develop
something ourselves) |
January:
| Development work begins |
| Target – Have the wire prediction model develop
(classification tree) |
February:
| Apply the model on data sets to see if the model
works |
| If problems exist with models, tweak model or
develop another solution |
| Develop an algorithm using the classification tree |
March:
| Develop an application that uses the classification
tree to predict wire lengths |
| Begin work on poster |
April:
| Presentation |
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