arch-beerWeekly Reading |
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Mrinmoy is presenting...
Aamer Jaleel and Bruce Jacob "Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions" HPCA 2005 (Please do not distribute outside Georgia Tech). PDF copy (accessible within GT network only) The use of large instruction windows coupled with aggressive out-of-order and prefetching capabilities has provided significant improvements in processor performance. This paper quantifies the effects of increased out-of-order aggressiveness on a processor memory ordering/consistency model as well as an application cache behavior. They observe that increasing reorder buffer sizes cause less than one third of issued memory instructions to be executed in actual program order. Increasing the reorder buffer size from 80 to 512 entries results in an increase in the frequency of memory traps by a factor of six and an increase in total execution overhead by 10-40%. These findings reveal that increased out-of-order capability can waste energy. Thus, to avoid wasting both energy and performance, this paper proposes a virtual load/store queue (VLSQ) within the existing physical load/store queue. The VLSQ reduces the reordering of memory instructions by limiting the number of memory instructions visible to the select and issue logic. The paper shows that VLSQs can reduce trap overhead, cache accesses, and cache misses by as much as 45%, 50%, and 15% respectively when compared to traditional load/store queues. For interested people, background information can be found here. |