arch-beerWeekly Reading |
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Kiran is presenting...
(1) Jahangir Hasan, Ankit Jalote, T.N. Vijaykumar, Carla Brodley "Balancing Resource Utilization to Mitigate Power Density in Processor Pipelines" MICRO 2005 (Please do not distribute outside Georgia Tech). PDF copy (accessible within GT network only) (2) Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea Ismail "Thermal Management of On-Chip Caches Through Power Density Minimization" MICRO 2005 (Please do not distribute outside Georgia Tech). PDF copy (accessible within GT network only) Abstract for (1): Power density is a growing problem in high-performance processors in which small, high-activity resources overheat. Two categories of techniques, temporal and spatial, can address power density in a processor. Temporal solutions slow computation and heating either through frequency and voltage scaling or through stopping computation long enough to allow the processor to cool; both degrade performance. Spatial solutions reduce heat by moving computation from a hot resource to an alternate resource (e.g., a spare ALU) to allow cooling. Spatial solutions are appealing because they have negligible impact on performance, but they require availability of spatial slack in the form of spare or underutilized resource copies. Previous work has not considered exploiting the spatial slack already existing within pipeline resource copies. Utilization can be quite asymmetric across resource copies, leaving some copies substantially cooler than others. We observe that asymmetric utilization within copies of three key back-end resources, the issue queue, register files, and ALUs, creates spatial slack opportunities. The authors balance asymmetry in the utilization of three key back-end resources, the issue queue, register files, and ALUs to reduce power density. Abstract for (2): Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. However, these techniques mostly ignore the effects of temperature on the power consumption. In this paper, the authors propose a thermal-aware cache power-down technique that minimizes the power density of the active parts by turning off alternating rows of memory cells instead of entire banks. The decrease in the power density lowers the temperature, which in return, reduces the leakage of the active parts. They propose a block permutation scheme that can be used during the design of caches to maximize the distance between blocks with consecutive addresses. By maximizing the distance between consecutively accessed blocks, the power density of the hot spots in the cache reduces, hence reducing the peak temperature. Both of the proposed architectures add no extra run-time penalty compared to the thermal-unaware power reduction schemes, yet they reduce the total energy consumption of a conventional cache by 53% and 5.6% on average, respectively. |