arch-beerWeekly Reading |
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Juno is presenting... Rakesh Kumar, Dean M. Tullsen, and Norman P. Jouppi "Core Architecture Optimization for Heterogeneous Chip Multiprocessors " PACT 2006 PDF copy (accessible within GT network only) PDF copy (accessible within GT network only) Previous studies have demonstrated the advantage of single-ISA heterogeneous muti-core architectures for power and performance. However, none of those studies examined how to design such a processor; instead, they started with an assumed combination of pre-exisiting cores. This work assumes the flexibility to design a multi-core architecture from the ground up and seeks to address the following question: what should be the characterestics of the cores for a heterogeneous multi-processor for the highest area or power efficiency? The study is done for varying degrees of thread-level parallelism and for different area and power budgets. The most efficient chip multiprocessors are shown to be heterogeneous, with each core customized to a different subset of application characterestics - no single core is necessarily well suited to all applications. The performance ordering of cores on such processors is different for different applications; there is only a partial ordering among cores in terms of resources and complexity. This methodology produces performance gains as high as 40%. The performance improvements come with the added cost of cutomization. Mani is also going to be presenting his ICCD talk. |