A Framework for Evaluating Architectural Issues of Parallel Systems

                        Anand Sivasubramaniam

                        College of Computing
                  Georgia Institute of Technology

                             Abstract

Parallel computing is becoming increasingly important to scientific 
advancement and economic development. Despite the promise of being able
to meet the increased computational needs of the future, the delivered 
performance of parallel machines often falls short of the projected peak 
performance.  Evaluating and analyzing the performance of a parallel 
application on an architecture to explain the disparity between projected 
and delivered performance has widespread applicability in parallel systems 
research.  But conducting such a study is hard due to the additional degrees
of freedom exhibited by these systems compared to their sequential
counterparts.  This thesis identifies performance metrics that give 
detailed information on parallel system performance and outlines a
framework that we have developed to quantify these metrics.  The framework 
uses an application-driven approach with a combination of experimental, 
simulation and analytical techniques.

The evaluation framework can be used to research a variety of issues in
parallel systems design which is illustrated with four case-studies. In 
the first, the scalability of parallel applications on shared memory 
and message-passing hardware platforms is studied and the results are used to 
enhance parallel system performance by application restructuring.  The second 
study illustrates the use of the framework in evaluating the validity of 
theoretical/analytical models that are used for abstracting features of 
parallel systems. The third study characterizes the communication bandwidth 
requirements of parallel applications and quantifies the necessary link 
bandwidth in the interconnection network for a desired level of performance.  
The last study focuses on minimizing/tolerating the network latency in the 
context of shared memory multiprocessors. Examining the communication 
characteristics of real applications, a set of explicit communication 
mechanisms is proposed and the framework is used to evaluate the performance
improvement. The last two studies are two different architectural solutions 
to the same problem, namely, lowering the communication overhead in an 
application.

  Committee:   
    Dr. Umakishore Ramachandran (chairman)
    Dr. H. Venkateswaran (co-advisor)
    Dr. Richard Fujimoto 
    Dr. Sudhakar Yalamanchili (EE)
    Dr. Mark Hill (Univ. of Wisconsin, Madison)