diff -uNr xen-unstable.hg/.config xen-arm-ver/.config --- xen-unstable.hg/.config 1969-12-31 19:00:00.000000000 -0500 +++ xen-arm-ver/.config 2008-11-14 12:12:22.000000000 -0500 @@ -0,0 +1,62 @@ +# +# Automatically generated make config: don't edit +# Xen version: +# Mon Nov 10 10:56:57 2008 +# +CONFIG_ARM=y + +# +# General Setup +# +# CONFIG_OPTIMIZE_FOR_SIZE is not set +# CONFIG_EABI_SUPPORT is not set + +# +# System Type +# +CONFIG_CPU_ISA_32V5=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_COPYPAGE_V4WB=y +CONFIG_CPU_ARM926T=y +CONFIG_MACHINE_VERSATILE=y +# CONFIG_PLATFORM_IMX21ADS is not set +CONFIG_PLATFORM_VERSATILEPB=y + +# +# Customize Memory Map +# +CONFIG_HYPERVISOR_BASE=0xFF000000 + +# +# Domain Memory Size +# +CONFIG_MEMMAP_GUEST_0_SIZE=0x02000000 +CONFIG_MEMMAP_GUEST_1_SIZE=0x01000000 +CONFIG_MEMMAP_GUEST_2_SIZE=0x01000000 +CONFIG_MEMMAP_GUEST_3_SIZE=0x00000000 + +# +# Image Max Size +# +CONFIG_MEMMAP_GUEST_0_ELF_MAX_SIZE=0x00400000 +CONFIG_MEMMAP_GUEST_1_ELF_MAX_SIZE=0x00400000 +CONFIG_MEMMAP_GUEST_2_ELF_MAX_SIZE=0x00400000 +CONFIG_MEMMAP_GUEST_3_ELF_MAX_SIZE=0x00400000 + +# +# Ram Disk Size +# +CONFIG_MEMMAP_GUEST_0_RAMDISK_SIZE=0x00400000 +CONFIG_MEMMAP_GUEST_1_RAMDISK_SIZE=0x00400000 +CONFIG_MEMMAP_GUEST_2_RAMDISK_SIZE=0x00400000 +CONFIG_MEMMAP_GUEST_3_RAMDISK_SIZE=0x00400000 + +# +# Security Support +# +# CONFIG_VMM_SECURITY is not set + +# +# Debugging and profiling Support +# +# CONFIG_DEBUG is not set diff -uNr xen-unstable.hg/Config.mk xen-arm-ver/Config.mk --- xen-unstable.hg/Config.mk 2008-11-14 15:45:58.000000000 -0500 +++ xen-arm-ver/Config.mk 2008-11-14 11:59:54.000000000 -0500 @@ -5,7 +5,7 @@ XEN_COMPILE_ARCH ?= $(shell uname -m | sed -e s/i.86/x86_32/) XEN_TARGET_ARCH ?= arm -XEN_TARGET_SUBARCH ?= imx21 +XEN_TARGET_SUBARCH ?= versatile XEN_TARGET_X86_PAE ?= n # Tools to run on system hosting the build @@ -15,8 +15,7 @@ # # Cross Tool chain configuration # -CROSS_COMPILE = /opt/arm-linux-4.1.1/bin/arm-linux- -#CROSS_COMPILE = /opt/arm-linux-3.4.4/bin/arm-linux- +CROSS_COMPILE = /opt/nicta/tools/gcc-3.4.4-glibc-2.3.5/arm-linux/bin/arm-linux- # # Target Configuration for Xen-ARM diff -uNr xen-unstable.hg/extras/mini-os-arm/arch/arm/arch-versatile/start.S xen-arm-ver/extras/mini-os-arm/arch/arm/arch-versatile/start.S --- xen-unstable.hg/extras/mini-os-arm/arch/arm/arch-versatile/start.S 1969-12-31 19:00:00.000000000 -0500 +++ xen-arm-ver/extras/mini-os-arm/arch/arm/arch-versatile/start.S 2008-11-03 19:34:59.000000000 -0500 @@ -0,0 +1,33 @@ +#include + +.section __xen_guest + .ascii "GUEST_OS=Mini-OS" + .ascii ",XEN_VER=xen-3.0" + .ascii ",LOADER=generic" + .ascii ",PT_MODE_WRITABLE" + .ascii ",SCID=0" + + .text +ENTRY(_start) + + /* + * Stack Setup for User Mode + * This code will cause abort exception + */ + ldr sp, __init_sp + + mov r0, r12 + + b start_kernel + +__init_sp: + .long __stack_end + 0x1000 + + .org 0x1000 +ENTRY(shared_info) + .fill 0x8000,1,0 @ 32KB + +.section ".bss.stack_aligned","w" +__stack_end: + .fill 0x1000,1,0 @ 8KB + diff -uNr xen-unstable.hg/extras/mini-os-arm/arch/arm/arch-versatile/versatile.lds xen-arm-ver/extras/mini-os-arm/arch/arm/arch-versatile/versatile.lds --- xen-unstable.hg/extras/mini-os-arm/arch/arm/arch-versatile/versatile.lds 1969-12-31 19:00:00.000000000 -0500 +++ xen-arm-ver/extras/mini-os-arm/arch/arm/arch-versatile/versatile.lds 2008-11-03 19:36:10.000000000 -0500 @@ -0,0 +1,58 @@ +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0xC0008000; + _text = .; /* Text and read-only data */ + .text : { + *(.text) + *(.gnu.warning) + } = 0x9090 + + _etext = .; /* End of text section */ + + .rodata : { *(.rodata) *(.rodata.*) } + + .data : { /* Data */ + *(.data) + CONSTRUCTORS + } + + _edata = .; /* End of data section */ + + . = ALIGN(8192); /* init_task */ + .data.init_task : { *(.data.init_task) } + + . = ALIGN(4096); + .data.page_aligned : { *(.data.idt) } + + . = ALIGN(32); + .data.cacheline_aligned : { *(.data.cacheline_aligned) } + + . = ALIGN(8*1024); + __bss_start = .; /* BSS */ + .bss : { + __stack_end = .; + *(.bss.stack_aligned) + __stack_start = .; + *(.bss.page_aligned) + *(.bss) + } + _end = . ; + + /* Sections to be discarded */ + /DISCARD/ : { + *(.text.exit) + *(.data.exit) + *(.exitcall.exit) + } + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } +} diff -uNr xen-unstable.hg/extras/mini-os-arm/Config.mk xen-arm-ver/extras/mini-os-arm/Config.mk --- xen-unstable.hg/extras/mini-os-arm/Config.mk 2008-11-14 15:45:58.000000000 -0500 +++ xen-arm-ver/extras/mini-os-arm/Config.mk 2008-11-03 19:42:20.000000000 -0500 @@ -15,12 +15,12 @@ # Cross Tool chain configuration # #CROSS_COMPILE = arm_v4t_le- -CROSS_COMPILE = /opt/arm_v4t_le/bin/arm_v4t_le- +CROSS_COMPILE = /opt/nicta/tools/gcc-3.4.4-glibc-2.3.5/arm-linux/bin/arm-linux- # # Target Configuration for Xeno-mini # -XENO_TARGET_SUBARCH = imx21 +XENO_TARGET_SUBARCH = versatile AS = $(CROSS_COMPILE)as LD = $(CROSS_COMPILE)ld diff -uNr xen-unstable.hg/Makefile xen-arm-ver/Makefile --- xen-unstable.hg/Makefile 2008-11-14 15:45:58.000000000 -0500 +++ xen-arm-ver/Makefile 2008-10-21 16:22:51.000000000 -0400 @@ -111,7 +111,7 @@ # clean doesn't do a kclean clean:: $(MAKE) -C xen clean - $(MAKE) -C tools clean +# $(MAKE) -C tools clean $(MAKE) -C docs clean # clean, but blow away kernel build tree plus tarballs diff -uNr xen-unstable.hg/xen/arch/arm/arch-versatile/Kconfig xen-arm-ver/xen/arch/arm/arch-versatile/Kconfig --- xen-unstable.hg/xen/arch/arm/arch-versatile/Kconfig 1969-12-31 19:00:00.000000000 -0500 +++ xen-arm-ver/xen/arch/arm/arch-versatile/Kconfig 2008-10-21 16:20:36.000000000 -0400 @@ -0,0 +1,5 @@ +config PLATFORM_VERSATILEPB + bool "ARM versatile_pb" + select MACHINE_VERSATILE + help + Say Y here if you are using the ARM versatile PB diff -uNr xen-unstable.hg/xen/arch/arm/arch-versatile/Makefile xen-arm-ver/xen/arch/arm/arch-versatile/Makefile --- xen-unstable.hg/xen/arch/arm/arch-versatile/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ xen-arm-ver/xen/arch/arm/arch-versatile/Makefile 2008-11-10 13:59:21.000000000 -0500 @@ -0,0 +1,8 @@ +include $(BASEDIR)/Rules.mk + +obj-y += platform.o +obj-y += versatilepb_serial.o +obj-y += versatilepb_irq.o +obj-y += versatilepb_time.o + +include $(BASEDIR)/Post.mk diff -uNr xen-unstable.hg/xen/arch/arm/arch-versatile/platform.c xen-arm-ver/xen/arch/arm/arch-versatile/platform.c --- xen-unstable.hg/xen/arch/arm/arch-versatile/platform.c 1969-12-31 19:00:00.000000000 -0500 +++ xen-arm-ver/xen/arch/arm/arch-versatile/platform.c 2008-11-14 13:42:18.000000000 -0500 @@ -0,0 +1,75 @@ +/* + * platform.c + * + * Copyright (C) 2008 Minsung Jang + * Minsung Jang < minsung@gatech.edu > + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public version 2 of License as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +/* + * What to do in platform.c is to complete plaform_setup() in start_xen + * - Register platform initializing function by DECLARE_PLATFORM_OP + * - Register platform halt function by DECLARE_PLATFORM_OP + * - memory_init -> system clk init -> uart init -> irq init -> timer init + */ + + +static void versatilepb_memory_init(void) +{ + register_memory_bank( MEMMAP_DRAM_ADDR, 64 * 1024 * 1024); +// register_memory_bank(0x04000000, 64 * 1024 * 1024); +} + + +/* + * Initializing/halt/query platform + */ +static void versatilepb_platform_setup(void) +{ + versatilepb_memory_init(); + versatilepb_uart_init(); + versatilepb_irq_init(); + versatilepb_timer_init(); +} + +DECLARE_PLATFORM_OP(platform_setup, versatilepb_platform_setup); + +static void versatilepb_platform_halt(int mode) +{ +} + +DECLARE_PLATFORM_OP(platform_halt, versatilepb_platform_halt); + + +static void versatilepb_platform_query(struct query_data *query) +{ + switch(query->type) { + case QUERY_MEMORY_DETAILS : break; + case QUERY_CPU_DETAILS : break; + default : break; + }; +} + +DECLARE_PLATFORM_OP(platform_query, versatilepb_platform_query); + + + + diff -uNr xen-unstable.hg/xen/arch/arm/arch-versatile/README xen-arm-ver/xen/arch/arm/arch-versatile/README --- xen-unstable.hg/xen/arch/arm/arch-versatile/README 1969-12-31 19:00:00.000000000 -0500 +++ xen-arm-ver/xen/arch/arm/arch-versatile/README 2008-11-14 15:44:23.000000000 -0500 @@ -0,0 +1,21 @@ + XenARM for ARM VersatilePB Board + +Nov/14/2008 Minsung Jang + +Introduction: +XenARM for ARM VersatilePB Board assumes it executes on top of u-boot, and +have been developed and tested on QEMU environment. Since current QEMU is not +properly emulating the flash memory of VersatilePB, you must apply patches +into QEMU and u-boot. +Please, refer http://thomas.enix.org/Blog-20081002153859-Technologie + +Limitation: +- Only supports upper 64MB of RAM on board (0x04000000-0x08000000) + in order to avoid the conflict with domain creation codes in XenARM. + I expect the conflict will be resolved by XenARM maintainers in near future. +- Impossible to use Secondary Interrupt Controller(SIC) + +Location of binaries (Physical Address) +- Xen 0x04008000 +- Mini-OS 1 0x05c00000 +- Mini-OS 2 0x06c00000 diff -uNr xen-unstable.hg/xen/arch/arm/arch-versatile/start.S xen-arm-ver/xen/arch/arm/arch-versatile/start.S --- xen-unstable.hg/xen/arch/arm/arch-versatile/start.S 1969-12-31 19:00:00.000000000 -0500 +++ xen-arm-ver/xen/arch/arm/arch-versatile/start.S 2008-11-14 11:57:33.000000000 -0500 @@ -0,0 +1,155 @@ +/* + * start.S + * + * Copyright (C) 2008 Minsung Jang + * < minsung@gatech.edu > + * + * Secure Xen on ARM architecture designed by Sang-bum Suh consists of + * Xen on ARM and the associated access control. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public version 2 of License as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + + .type text, %function +ENTRY(text) + msr cpsr_c, #PSR_STATUS_F | PSR_STATUS_I | PSR_MODE_SVC + + adr r1, __SRA_INFO + str r0, [r1, #0] + + mcr p15, 0, ip, c7, c7, 0 @ Invalidate I, D caches & BTB + mcr p15, 0, ip, c7, c10, 4 @ Drain Write Buffer + mcr p15, 0, ip, c8, c7, 0 @ Invalidate I, D TLBs + + /* clear page table area */ +pgd_setup: + adr r0, text + mov r1, r0 + sub r0, r0, #0x4000 + mov r2, #0 +1: str r2, [r1, #-4]! + str r2, [r1, #-4]! + str r2, [r1, #-4]! + str r2, [r1, #-4]! + cmp r0, r1 + bne 1b + + adr r4, mem_map_table + b 2f + +1: + str r3, [r0, r2] + add r2, r2, #4 + add r3, r3, #0x100000 + adds r1, r1, #-1 + bhi 1b +2: + ldmia r4!, {r1, r2, r3} + cmp r1, #0 + bne 1b + +dac_setup: + mov r5, #(DOMAIN_VALUE(DOMAIN_SUPERVISOR, DOMAIN_MANAGER) | \ + DOMAIN_VALUE(DOMAIN_HYPERVISOR, DOMAIN_MANAGER) | \ + DOMAIN_VALUE(DOMAIN_USER, DOMAIN_MANAGER) | \ + DOMAIN_VALUE(DOMAIN_IO, DOMAIN_CLIENT)) + + mcr p15, 0, r5, c3, c0, 0 @ Load DAC + + mcr p15, 0, r0, c2, c0, 0 @ Load page table pointer + mrc p15, 0, r6, c1, c0, 0 + + orr r6, r6, #CR_M @ Enable Memory Management Unit + orr r6, r6, #CR_C @ Enable Data Cache + orr r6, r6, #CR_W @ Enable Write Buffer + orr r6, r6, #CR_I @ Enable Instruction Cache + bic r6, r6, #CR_V @ Use Low Vector Table(0x0000:0000) + + mcr p15, 0, r6, c1, c0, 0 @ Turn on MMU + mrc p15, 0, r3, c0, c0, 0 + mov r0, r0 + mov r0, r0 + mov r0, r0 + + mcr p15, 0, ip, c7, c7, 0 @ Invalidate I, D caches & BTB + mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer + mcr p15, 0, ip, c8, c7, 0 @ Invalidate I, D TLBs + + b clear_bss + +1: .word __bss_start + .word _end + +clear_bss: + adr r0, 1b + ldmia r0, {r1, r2} + mov r0, #0 +1: + str r0, [r1], #4 + str r0, [r1], #4 + str r0, [r1], #4 + str r0, [r1], #4 + cmp r1, r2 + blo 1b + +stack_setup: + msr cpsr_c, #PSR_MODE_IRQ | PSR_STATUS_I | PSR_STATUS_F + ldr sp, =(irq_stack + STACK_SIZE) + + msr cpsr_c, #PSR_MODE_ABT | PSR_STATUS_I | PSR_STATUS_F + ldr sp, =(abt_stack + STACK_SIZE) + + msr cpsr_c, #PSR_MODE_UND | PSR_STATUS_I | PSR_STATUS_F + ldr sp, =(und_stack + STACK_SIZE) + + msr cpsr_c, #PSR_MODE_SVC | PSR_STATUS_I | PSR_STATUS_F + ldr sp, =(svc_stack + STACK_SIZE) + + adr r12, 1f + ldmia r12, {lr, pc} + +1: + .long 0 + .long start_xen + + +/* Reflect on arm versatile_pb memory map */ +/* VA PA size attr */ +mem_map_table: + MAP_ENTRY(0x04000000, 0x04000000, 64, PDE_TYPE_HYPERVISOR) /* Idle domain -> 1:1 mapping */ + MAP_ENTRY(0xFF000000, 0x04000000, 2, PDE_TYPE_HYPERVISOR) /* Xen */ + MAP_ENTRY(0xF1000000, 0x10000000, 2, PDE_TYPE_IO) /* Versatile I/O address */ + MAP_ENTRY(0,0,0,0) + +ENTRY(sra_info_ptr) +__SRA_INFO: + .long 0 + + .section .bss.stack_aligned,"w" +ENTRY(svc_stack) + .fill STACK_SIZE,1,0 +ENTRY(irq_stack) + .fill STACK_SIZE,1,0 +ENTRY(abt_stack) + .fill STACK_SIZE,1,0 +ENTRY(und_stack) + .fill STACK_SIZE,1,0 diff -uNr xen-unstable.hg/xen/arch/arm/arch-versatile/versatilepb_irq.c xen-arm-ver/xen/arch/arm/arch-versatile/versatilepb_irq.c --- xen-unstable.hg/xen/arch/arm/arch-versatile/versatilepb_irq.c 1969-12-31 19:00:00.000000000 -0500 +++ xen-arm-ver/xen/arch/arm/arch-versatile/versatilepb_irq.c 2008-11-14 13:44:33.000000000 -0500 @@ -0,0 +1,105 @@ +/* + * versatilepb_irq.c + * + * Copyright (C) 2008 Minsung Jang + * Minsung Jang < minsung@gatech.edu > + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public version 2 of License as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define VERSATILE_VIC_BASE 0x10140000 /* PA of Verctored interrupt controller */ +#define VERSATILE_SIC_BASE 0x10003000 /* PA of Secondary interrupt controller */ +#define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE) +#define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE) +#define PIC_MASK 0xFFD00000 + +/* + - Most codes are from Linux 2.6.27. + - To do: This file contains only VIC related codes, so if you want to use SIC, write yourself + */ + +extern struct irqdesc irq_desc[NR_IRQS]; + +static void versatile_vic_mask_irq(unsigned int irq) +{ + IO_WRITE ( VA_VIC_BASE + VIC_INT_ENABLE_CLEAR, 1< + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public version 2 of License as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#define VA_SERIAL0_BASE __io_address(0x101F1000 /* PA */) +#define VA_SERIAL1_BASE __io_address(0x101F2000 /* PA */) +#define CONSOLE_PORT 0 +#define baudRate 38400 +#define CONFIG_PL011_CLOCK 24000000 +#define CONFIG_PL01x_PORTS { (void *)0xf11f1000, (void *)0xf11f2000 } +#define NUM_PORTS (sizeof(port)/sizeof(port[0])) + +volatile unsigned char *const port[] = CONFIG_PL01x_PORTS; + +/* + * Most codes are from arm versatile support of U-boot + */ + + +void pl011_putc (int portnum, char c) +{ + /* Wait until there is space in the FIFO */ + while ( IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF); + + /* Send the character */ + IO_WRITE(port[portnum] + UART_PL01x_DR, c); +} + +static int pl011_getc (int portnum) +{ + unsigned int data; + + /* Wait until there is data in the FIFO */ + while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE); + + data = IO_READ (port[portnum] + UART_PL01x_DR); + + /* Check for an error flag */ + if (data & 0xFFFFFF00) { + /* Clear the error */ + IO_WRITE(port[portnum] + UART_PL01x_ECR, 0xFFFFFFFF); + return -1; + } + + return (int) data; +} + +static void versatilepb_uart_putc (struct serial_port *port, const char c) +{ + if (c == '\n') + pl011_putc (CONSOLE_PORT, '\r'); + + pl011_putc (CONSOLE_PORT, c); +} + + + +static int versatilepb_uart_getc (struct serial_port *port, char *pc) +{ + return pl011_getc (CONSOLE_PORT); +} + + + +static struct uart_driver versatilepb_uart_driver = { + .putc = versatilepb_uart_putc, + .getc = versatilepb_uart_getc +}; + +static struct ns16550_defaults versatilepb_uart_params = { + .baud = BAUD_AUTO, + .data_bits = 8, + .parity = 'n', + .stop_bits = 1 +}; + +void versatilepb_uart_init (void) +{ + unsigned int temp; + unsigned int divider; + unsigned int remainder; + unsigned int fraction; + + /* + ** First, disable everything. + */ + IO_WRITE (port[CONSOLE_PORT] + UART_PL011_CR, 0x0); + + /* + ** Set baud rate + ** + ** IBRD = UART_CLK / (16 * BAUD_RATE) + ** FBRD = ROUND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE)) + */ + temp = 16 * baudRate; + divider = CONFIG_PL011_CLOCK / temp; + remainder = CONFIG_PL011_CLOCK % temp; + temp = (8 * remainder) / baudRate; + fraction = (temp >> 1) + (temp & 1); + + IO_WRITE (port[CONSOLE_PORT] + UART_PL011_IBRD, divider); + IO_WRITE (port[CONSOLE_PORT] + UART_PL011_FBRD, fraction); + + /* + ** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled. + */ + IO_WRITE (port[CONSOLE_PORT] + UART_PL011_LCRH, + (UART_PL011_LCRH_WLEN_8 | 0 << 4)); //fifo DISABLE + +/* IO_WRITE (port[CONSOLE_PORT] + UART_PL011_LCRH, + (UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN)); */ + + /* + ** Finally, enable the UART + */ + IO_WRITE (port[CONSOLE_PORT] + UART_PL011_CR, + (UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | + UART_PL011_CR_RXE)); + + serial_register_uart(0, &versatilepb_uart_driver, &versatilepb_uart_params); +} diff -uNr xen-unstable.hg/xen/arch/arm/arch-versatile/versatilepb_time.c xen-arm-ver/xen/arch/arm/arch-versatile/versatilepb_time.c --- xen-unstable.hg/xen/arch/arm/arch-versatile/versatilepb_time.c 1969-12-31 19:00:00.000000000 -0500 +++ xen-arm-ver/xen/arch/arm/arch-versatile/versatilepb_time.c 2008-11-14 13:44:13.000000000 -0500 @@ -0,0 +1,103 @@ +/* + * versatilepb_time.c + * + * Copyright (C) 2008 Minsung Jang + * Minsung Jang < minsung@gatech.edu > + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public version 2 of License as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE) +#define TIMER1_VA_BASE (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20) +#define TIMER2_VA_BASE __io_address(VERSATILE_TIMER2_3_BASE) +#define TIMER3_VA_BASE (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20) + + +/* + * Most codes are from Linux 2.6.27. + * Timer3 is used for timer tick. + */ + +extern void timer_tick(struct cpu_user_regs *regs); + +irqreturn_t versatilepb_timer_interrupt(int irq, void *dev_id, struct cpu_user_regs *regs) +{ + /* Increment jiffies */ + timer_tick(regs); + /* Clear bit */ + IO_WRITE(TIMER3_VA_BASE + TIMER_INTCLR,1); + raise_softirq(TIMER_SOFTIRQ); + + return IRQ_HANDLED; +} + +static struct irqaction versatilepb_timer_irq = { + .name = "VersatilePB timer tick", + .dev_id = NULL, + .handler = versatilepb_timer_interrupt +}; + +void versatilepb_timer_init (void) +{ + u32 val; + + /* + * set clock frequency: + * VERSATILE_REFCLK is 32KHz + * VERSATILE_TIMCLK is 1MHz + */ + val = IO_READ(__io_address(VERSATILE_SCTL_BASE)); + IO_WRITE(__io_address(VERSATILE_SCTL_BASE), + (VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) | + (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) | + (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) | + (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val); + + /* + * Initialise to a known state (all timers off) + */ + IO_WRITE(TIMER0_VA_BASE + TIMER_CTRL,0); + IO_WRITE(TIMER1_VA_BASE + TIMER_CTRL,0); + IO_WRITE(TIMER2_VA_BASE + TIMER_CTRL,0); + IO_WRITE(TIMER3_VA_BASE + TIMER_CTRL,0); + + /* Register IRQ */ + setup_irq(IRQ_TIMERINT2_3, &versatilepb_timer_irq); + + /* Enabling Timer0 */ + IO_WRITE(TIMER3_VA_BASE + TIMER_CTRL,0); + IO_WRITE(TIMER3_VA_BASE + TIMER_LOAD,LATCH-1); + IO_WRITE(TIMER3_VA_BASE + TIMER_VALUE,LATCH-1); + IO_WRITE(TIMER3_VA_BASE+TIMER_CTRL, + TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC|TIMER_CTRL_IE); + +} + + + + diff -uNr xen-unstable.hg/xen/arch/arm/defconfig/defconfig_versatilepb xen-arm-ver/xen/arch/arm/defconfig/defconfig_versatilepb --- xen-unstable.hg/xen/arch/arm/defconfig/defconfig_versatilepb 1969-12-31 19:00:00.000000000 -0500 +++ xen-arm-ver/xen/arch/arm/defconfig/defconfig_versatilepb 2008-11-10 14:01:26.000000000 -0500 @@ -0,0 +1,62 @@ +# +# Automatically generated make config: don't edit +# Xen version: +# Mon Nov 10 10:56:57 2008 +# +CONFIG_ARM=y + +# +# General Setup +# +# CONFIG_OPTIMIZE_FOR_SIZE is not set +# CONFIG_EABI_SUPPORT is not set + +# +# System Type +# +CONFIG_CPU_ISA_32V5=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_COPYPAGE_V4WB=y +CONFIG_CPU_ARM926T=y +CONFIG_MACHINE_VERSATILE=y +# CONFIG_PLATFORM_IMX21ADS is not set +CONFIG_PLATFORM_VERSATILEPB=y + +# +# Customize Memory Map +# +CONFIG_HYPERVISOR_BASE=0xFF000000 + +# +# Domain Memory Size +# +CONFIG_MEMMAP_GUEST_0_SIZE=0x02000000 +CONFIG_MEMMAP_GUEST_1_SIZE=0x01000000 +CONFIG_MEMMAP_GUEST_2_SIZE=0x01000000 +CONFIG_MEMMAP_GUEST_3_SIZE=0x00000000 + +# +# Image Max Size +# +CONFIG_MEMMAP_GUEST_0_ELF_MAX_SIZE=0x00400000 +CONFIG_MEMMAP_GUEST_1_ELF_MAX_SIZE=0x00400000 +CONFIG_MEMMAP_GUEST_2_ELF_MAX_SIZE=0x00400000 +CONFIG_MEMMAP_GUEST_3_ELF_MAX_SIZE=0x00400000 + +# +# Ram Disk Size +# +CONFIG_MEMMAP_GUEST_0_RAMDISK_SIZE=0x00400000 +CONFIG_MEMMAP_GUEST_1_RAMDISK_SIZE=0x00400000 +CONFIG_MEMMAP_GUEST_2_RAMDISK_SIZE=0x00400000 +CONFIG_MEMMAP_GUEST_3_RAMDISK_SIZE=0x00400000 + +# +# Security Support +# +# CONFIG_VMM_SECURITY is not set + +# +# Debugging and profiling Support +# +# CONFIG_DEBUG is not set diff -uNr xen-unstable.hg/xen/arch/arm/Kconfig xen-arm-ver/xen/arch/arm/Kconfig --- xen-unstable.hg/xen/arch/arm/Kconfig 2008-11-14 15:45:58.000000000 -0500 +++ xen-arm-ver/xen/arch/arm/Kconfig 2008-11-14 12:00:04.000000000 -0500 @@ -32,10 +32,14 @@ bool select CPU_ARM926T +config MACHINE_VERSATILE + bool + select CPU_ARM926T + choice prompt "Select target platform" - source "arch/arm/arch-imx21/Kconfig" +source "arch/arm/arch-versatile/Kconfig" endchoice endmenu diff -uNr xen-unstable.hg/xen/arch/arm/Rules.mk xen-arm-ver/xen/arch/arm/Rules.mk --- xen-unstable.hg/xen/arch/arm/Rules.mk 2008-11-14 15:45:58.000000000 -0500 +++ xen-arm-ver/xen/arch/arm/Rules.mk 2008-11-09 16:54:25.000000000 -0500 @@ -8,7 +8,8 @@ supervisor_mode_kernel ?= n -CFLAGS += -nostdinc -fno-builtin -fno-common -fno-strict-aliasing +#CFLAGS += -nostdinc -fno-builtin -fno-common -fno-strict-aliasing +CFLAGS += -nostdinc -fno-builtin -fno-common -fno-strict-aliasing -g CFLAGS += -iwithprefix include -Wno-pointer-arith -pipe CFLAGS += -I$(BASEDIR)/include -I$(BASEDIR)/include/security -I$(BASEDIR)/include/security/crypto @@ -16,6 +17,7 @@ CFLAGS +=-mabi=aapcs-linux -mno-thumb-interwork endif +machine-$(CONFIG_MACHINE_VERSATILE) := versatile machine-$(CONFIG_MACHINE_IMX21) := imx21 TARGET_MACHINE := $(machine-y) diff -uNr xen-unstable.hg/xen/arch/arm/xen/entry.S xen-arm-ver/xen/arch/arm/xen/entry.S --- xen-unstable.hg/xen/arch/arm/xen/entry.S 2008-11-14 15:45:58.000000000 -0500 +++ xen-arm-ver/xen/arch/arm/xen/entry.S 2008-11-14 12:14:36.000000000 -0500 @@ -72,8 +72,9 @@ .align 5 __irq_svc: save_svc_context - - +#ifdef CONFIG_MACHINE_VERSATILE + get_irqnr_preamble r5, lr @ minsung +#endif 1: get_irqnr_and_base r0, r6, r5, lr movne r1, sp @@ -212,7 +213,9 @@ cmp r1, #0x10 streq r2, [r0, #OFFSET_VUSP] strne r2, [r0, #OFFSET_VKSP] - +#ifdef CONFIG_MACHINE_VERSATILE + get_irqnr_preamble r5, lr @ minsung +#endif 1: get_irqnr_and_base r0, r6, r5, lr movne r1, sp diff -uNr xen-unstable.hg/xen/include/asm-arm/arch-versatile/config.h xen-arm-ver/xen/include/asm-arm/arch-versatile/config.h --- xen-unstable.hg/xen/include/asm-arm/arch-versatile/config.h 1969-12-31 19:00:00.000000000 -0500 +++ xen-arm-ver/xen/include/asm-arm/arch-versatile/config.h 2008-11-14 13:42:26.000000000 -0500 @@ -0,0 +1,40 @@ +/* + * arch/arm/mach-versatile/include/mach/memory.h + * + * Copyright (C) 2003 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +#define HZ 100 + +/* Physical DRAM offset */ +#define PHYS_OFFSET (0x04000000UL) // don't use lower 64MB + +/* AS PARAMS */ +#define __PAGE_OFFSET (0xFB000000UL) +#define IO_OFFSET (0xD1000000UL) + +#define IDLE_PG_TABLE_ADDR (0x04004000UL) + +#define MEMMAP_DRAM_ADDR PHYS_OFFSET +#define MEMMAP_DRAM_SIZE 0x04000000 +#define MEMMAP_NOR_ADDR 0x34000000 +#define MEMMAP_NOR_SIZE 0x04000000 + + +#endif diff -uNr xen-unstable.hg/xen/include/asm-arm/arch-versatile/debug-macro.S xen-arm-ver/xen/include/asm-arm/arch-versatile/debug-macro.S --- xen-unstable.hg/xen/include/asm-arm/arch-versatile/debug-macro.S 1969-12-31 19:00:00.000000000 -0500 +++ xen-arm-ver/xen/include/asm-arm/arch-versatile/debug-macro.S 2008-10-24 15:01:04.000000000 -0400 @@ -0,0 +1,23 @@ +/* arch/arm/mach-versatile/include/mach/debug-macro.S + * + * Debugging macro include header + * + * Copyright (C) 1994-1999 Russell King + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * +*/ + + .macro addruart,rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + moveq \rx, #0x10000000 + movne \rx, #0xf1000000 @ virtual base + orr \rx, \rx, #0x001F0000 + orr \rx, \rx, #0x00001000 + .endm + +#include diff -uNr xen-unstable.hg/xen/include/asm-arm/arch-versatile/dma.h xen-arm-ver/xen/include/asm-arm/arch-versatile/dma.h --- xen-unstable.hg/xen/include/asm-arm/arch-versatile/dma.h 1969-12-31 19:00:00.000000000 -0500 +++ xen-arm-ver/xen/include/asm-arm/arch-versatile/dma.h 2008-10-24 15:01:04.000000000 -0400 @@ -0,0 +1,20 @@ +/* + * arch/arm/mach-versatile/include/mach/dma.h + * + * Copyright (C) 2003 ARM Limited. + * Copyright (C) 1997,1998 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ diff -uNr xen-unstable.hg/xen/include/asm-arm/arch-versatile/entry-macro.S xen-arm-ver/xen/include/asm-arm/arch-versatile/entry-macro.S --- xen-unstable.hg/xen/include/asm-arm/arch-versatile/entry-macro.S 1969-12-31 19:00:00.000000000 -0500 +++ xen-arm-ver/xen/include/asm-arm/arch-versatile/entry-macro.S 2008-11-11 20:30:42.000000000 -0500 @@ -0,0 +1,48 @@ +/* + * arch/arm/mach-versatile/include/mach/entry-macro.S + * + * Low-level IRQ helper macros for Versatile platforms + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ +/* #include + *#include + */ + +#include "hardware.h" +#include "vic.h" + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + ldr \base, =IO_ADDRESS(VERSATILE_VIC_BASE) + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get masked status + mov \irqnr, #0 + teq \irqstat, #0 + beq 1003f + +1001: tst \irqstat, #15 + bne 1002f + add \irqnr, \irqnr, #4 + movs \irqstat, \irqstat, lsr #4 + bne 1001b +1002: tst \irqstat, #1 + bne 1003f + add \irqnr, \irqnr, #1 + movs \irqstat, \irqstat, lsr #1 + bne 1002b +1003: /* EQ will be set if no irqs pending */ + +@ clz \irqnr, \irqstat +@1003: /* EQ will be set if we reach MAXIRQNUM */ + .endm + diff -uNr xen-unstable.hg/xen/include/asm-arm/arch-versatile/hardware.h xen-arm-ver/xen/include/asm-arm/arch-versatile/hardware.h --- xen-unstable.hg/xen/include/asm-arm/arch-versatile/hardware.h 1969-12-31 19:00:00.000000000 -0500 +++ xen-arm-ver/xen/include/asm-arm/arch-versatile/hardware.h 2008-10-27 12:07:26.000000000 -0400 @@ -0,0 +1,52 @@ +/* + * arch/arm/mach-versatile/include/mach/hardware.h + * + * This file contains the hardware definitions of the Versatile boards. + * + * Copyright (C) 2003 ARM Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include +#include "platform.h" + +/* + * PCI space virtual addresses + */ +#define VERSATILE_PCI_VIRT_BASE (void __iomem *)0xe8000000ul +#define VERSATILE_PCI_CFG_VIRT_BASE (void __iomem *)0xe9000000ul + +#if 0 +#define VERSATILE_PCI_VIRT_MEM_BASE0 0xf4000000 +#define VERSATILE_PCI_VIRT_MEM_BASE1 0xf5000000 +#define VERSATILE_PCI_VIRT_MEM_BASE2 0xf6000000 + +#define PCIO_BASE VERSATILE_PCI_VIRT_MEM_BASE0 +#define PCIMEM_BASE VERSATILE_PCI_VIRT_MEM_BASE1 +#endif + +/* CIK guesswork */ +#define PCIBIOS_MIN_IO 0x44000000 +#define PCIBIOS_MIN_MEM 0x50000000 + +#define pcibios_assign_all_busses() 1 + +/* macro to get at IO space when running virtually */ +#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000) + +#endif diff -uNr xen-unstable.hg/xen/include/asm-arm/arch-versatile/io.h xen-arm-ver/xen/include/asm-arm/arch-versatile/io.h --- xen-unstable.hg/xen/include/asm-arm/arch-versatile/io.h 1969-12-31 19:00:00.000000000 -0500 +++ xen-arm-ver/xen/include/asm-arm/arch-versatile/io.h 2008-11-14 13:38:49.000000000 -0500 @@ -0,0 +1,38 @@ +/* + * arch/arm/mach-versatile/include/mach/io.h + * + * Copyright (C) 2003 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff +static inline void __iomem *__io(unsigned long addr) +{ + return (void __iomem *)addr; +} +#define __io(a) __io(a) +#define __mem_pci(a) (a) + +#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000) +#define __io_address(n) __io(IO_ADDRESS(n)) +#define IO_WRITE(addr, val) (*(volatile unsigned int *)(addr) = (val)) +#define IO_READ(addr) (*(volatile unsigned int *)(addr)) + + + +#endif diff -uNr xen-unstable.hg/xen/include/asm-arm/arch-versatile/irqs.h xen-arm-ver/xen/include/asm-arm/arch-versatile/irqs.h --- xen-unstable.hg/xen/include/asm-arm/arch-versatile/irqs.h 1969-12-31 19:00:00.000000000 -0500 +++ xen-arm-ver/xen/include/asm-arm/arch-versatile/irqs.h 2008-11-11 19:28:59.000000000 -0500 @@ -0,0 +1,211 @@ +/* + * arch/arm/mach-versatile/include/mach/irqs.h + * + * Copyright (C) 2003 ARM Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include "platform.h" + +/* + * IRQ interrupts definitions are the same as the INT definitions + * held within platform.h + */ +#define IRQ_VIC_START 0 +#define IRQ_WDOGINT (IRQ_VIC_START + INT_WDOGINT) +#define IRQ_SOFTINT (IRQ_VIC_START + INT_SOFTINT) +#define IRQ_COMMRx (IRQ_VIC_START + INT_COMMRx) +#define IRQ_COMMTx (IRQ_VIC_START + INT_COMMTx) +#define IRQ_TIMERINT0_1 (IRQ_VIC_START + INT_TIMERINT0_1) +#define IRQ_TIMERINT2_3 (IRQ_VIC_START + INT_TIMERINT2_3) +#define IRQ_GPIOINT0 (IRQ_VIC_START + INT_GPIOINT0) +#define IRQ_GPIOINT1 (IRQ_VIC_START + INT_GPIOINT1) +#define IRQ_GPIOINT2 (IRQ_VIC_START + INT_GPIOINT2) +#define IRQ_GPIOINT3 (IRQ_VIC_START + INT_GPIOINT3) +#define IRQ_RTCINT (IRQ_VIC_START + INT_RTCINT) +#define IRQ_SSPINT (IRQ_VIC_START + INT_SSPINT) +#define IRQ_UARTINT0 (IRQ_VIC_START + INT_UARTINT0) +#define IRQ_UARTINT1 (IRQ_VIC_START + INT_UARTINT1) +#define IRQ_UARTINT2 (IRQ_VIC_START + INT_UARTINT2) +#define IRQ_SCIINT (IRQ_VIC_START + INT_SCIINT) +#define IRQ_CLCDINT (IRQ_VIC_START + INT_CLCDINT) +#define IRQ_DMAINT (IRQ_VIC_START + INT_DMAINT) +#define IRQ_PWRFAILINT (IRQ_VIC_START + INT_PWRFAILINT) +#define IRQ_MBXINT (IRQ_VIC_START + INT_MBXINT) +#define IRQ_GNDINT (IRQ_VIC_START + INT_GNDINT) +#define IRQ_VICSOURCE21 (IRQ_VIC_START + INT_VICSOURCE21) +#define IRQ_VICSOURCE22 (IRQ_VIC_START + INT_VICSOURCE22) +#define IRQ_VICSOURCE23 (IRQ_VIC_START + INT_VICSOURCE23) +#define IRQ_VICSOURCE24 (IRQ_VIC_START + INT_VICSOURCE24) +#define IRQ_VICSOURCE25 (IRQ_VIC_START + INT_VICSOURCE25) +#define IRQ_VICSOURCE26 (IRQ_VIC_START + INT_VICSOURCE26) +#define IRQ_VICSOURCE27 (IRQ_VIC_START + INT_VICSOURCE27) +#define IRQ_VICSOURCE28 (IRQ_VIC_START + INT_VICSOURCE28) +#define IRQ_VICSOURCE29 (IRQ_VIC_START + INT_VICSOURCE29) +#define IRQ_VICSOURCE30 (IRQ_VIC_START + INT_VICSOURCE30) +#define IRQ_VICSOURCE31 (IRQ_VIC_START + INT_VICSOURCE31) +#define IRQ_VIC_END (IRQ_VIC_START + 31) + +#define IRQMASK_WDOGINT INTMASK_WDOGINT +#define IRQMASK_SOFTINT INTMASK_SOFTINT +#define IRQMASK_COMMRx INTMASK_COMMRx +#define IRQMASK_COMMTx INTMASK_COMMTx +#define IRQMASK_TIMERINT0_1 INTMASK_TIMERINT0_1 +#define IRQMASK_TIMERINT2_3 INTMASK_TIMERINT2_3 +#define IRQMASK_GPIOINT0 INTMASK_GPIOINT0 +#define IRQMASK_GPIOINT1 INTMASK_GPIOINT1 +#define IRQMASK_GPIOINT2 INTMASK_GPIOINT2 +#define IRQMASK_GPIOINT3 INTMASK_GPIOINT3 +#define IRQMASK_RTCINT INTMASK_RTCINT +#define IRQMASK_SSPINT INTMASK_SSPINT +#define IRQMASK_UARTINT0 INTMASK_UARTINT0 +#define IRQMASK_UARTINT1 INTMASK_UARTINT1 +#define IRQMASK_UARTINT2 INTMASK_UARTINT2 +#define IRQMASK_SCIINT INTMASK_SCIINT +#define IRQMASK_CLCDINT INTMASK_CLCDINT +#define IRQMASK_DMAINT INTMASK_DMAINT +#define IRQMASK_PWRFAILINT INTMASK_PWRFAILINT +#define IRQMASK_MBXINT INTMASK_MBXINT +#define IRQMASK_GNDINT INTMASK_GNDINT +#define IRQMASK_VICSOURCE21 INTMASK_VICSOURCE21 +#define IRQMASK_VICSOURCE22 INTMASK_VICSOURCE22 +#define IRQMASK_VICSOURCE23 INTMASK_VICSOURCE23 +#define IRQMASK_VICSOURCE24 INTMASK_VICSOURCE24 +#define IRQMASK_VICSOURCE25 INTMASK_VICSOURCE25 +#define IRQMASK_VICSOURCE26 INTMASK_VICSOURCE26 +#define IRQMASK_VICSOURCE27 INTMASK_VICSOURCE27 +#define IRQMASK_VICSOURCE28 INTMASK_VICSOURCE28 +#define IRQMASK_VICSOURCE29 INTMASK_VICSOURCE29 +#define IRQMASK_VICSOURCE30 INTMASK_VICSOURCE30 +#define IRQMASK_VICSOURCE31 INTMASK_VICSOURCE31 + +/* + * FIQ interrupts definitions are the same as the INT definitions. + */ +#define FIQ_WDOGINT INT_WDOGINT +#define FIQ_SOFTINT INT_SOFTINT +#define FIQ_COMMRx INT_COMMRx +#define FIQ_COMMTx INT_COMMTx +#define FIQ_TIMERINT0_1 INT_TIMERINT0_1 +#define FIQ_TIMERINT2_3 INT_TIMERINT2_3 +#define FIQ_GPIOINT0 INT_GPIOINT0 +#define FIQ_GPIOINT1 INT_GPIOINT1 +#define FIQ_GPIOINT2 INT_GPIOINT2 +#define FIQ_GPIOINT3 INT_GPIOINT3 +#define FIQ_RTCINT INT_RTCINT +#define FIQ_SSPINT INT_SSPINT +#define FIQ_UARTINT0 INT_UARTINT0 +#define FIQ_UARTINT1 INT_UARTINT1 +#define FIQ_UARTINT2 INT_UARTINT2 +#define FIQ_SCIINT INT_SCIINT +#define FIQ_CLCDINT INT_CLCDINT +#define FIQ_DMAINT INT_DMAINT +#define FIQ_PWRFAILINT INT_PWRFAILINT +#define FIQ_MBXINT INT_MBXINT +#define FIQ_GNDINT INT_GNDINT +#define FIQ_VICSOURCE21 INT_VICSOURCE21 +#define FIQ_VICSOURCE22 INT_VICSOURCE22 +#define FIQ_VICSOURCE23 INT_VICSOURCE23 +#define FIQ_VICSOURCE24 INT_VICSOURCE24 +#define FIQ_VICSOURCE25 INT_VICSOURCE25 +#define FIQ_VICSOURCE26 INT_VICSOURCE26 +#define FIQ_VICSOURCE27 INT_VICSOURCE27 +#define FIQ_VICSOURCE28 INT_VICSOURCE28 +#define FIQ_VICSOURCE29 INT_VICSOURCE29 +#define FIQ_VICSOURCE30 INT_VICSOURCE30 +#define FIQ_VICSOURCE31 INT_VICSOURCE31 + + +#define FIQMASK_WDOGINT INTMASK_WDOGINT +#define FIQMASK_SOFTINT INTMASK_SOFTINT +#define FIQMASK_COMMRx INTMASK_COMMRx +#define FIQMASK_COMMTx INTMASK_COMMTx +#define FIQMASK_TIMERINT0_1 INTMASK_TIMERINT0_1 +#define FIQMASK_TIMERINT2_3 INTMASK_TIMERINT2_3 +#define FIQMASK_GPIOINT0 INTMASK_GPIOINT0 +#define FIQMASK_GPIOINT1 INTMASK_GPIOINT1 +#define FIQMASK_GPIOINT2 INTMASK_GPIOINT2 +#define FIQMASK_GPIOINT3 INTMASK_GPIOINT3 +#define FIQMASK_RTCINT INTMASK_RTCINT +#define FIQMASK_SSPINT INTMASK_SSPINT +#define FIQMASK_UARTINT0 INTMASK_UARTINT0 +#define FIQMASK_UARTINT1 INTMASK_UARTINT1 +#define FIQMASK_UARTINT2 INTMASK_UARTINT2 +#define FIQMASK_SCIINT INTMASK_SCIINT +#define FIQMASK_CLCDINT INTMASK_CLCDINT +#define FIQMASK_DMAINT INTMASK_DMAINT +#define FIQMASK_PWRFAILINT INTMASK_PWRFAILINT +#define FIQMASK_MBXINT INTMASK_MBXINT +#define FIQMASK_GNDINT INTMASK_GNDINT +#define FIQMASK_VICSOURCE21 INTMASK_VICSOURCE21 +#define FIQMASK_VICSOURCE22 INTMASK_VICSOURCE22 +#define FIQMASK_VICSOURCE23 INTMASK_VICSOURCE23 +#define FIQMASK_VICSOURCE24 INTMASK_VICSOURCE24 +#define FIQMASK_VICSOURCE25 INTMASK_VICSOURCE25 +#define FIQMASK_VICSOURCE26 INTMASK_VICSOURCE26 +#define FIQMASK_VICSOURCE27 INTMASK_VICSOURCE27 +#define FIQMASK_VICSOURCE28 INTMASK_VICSOURCE28 +#define FIQMASK_VICSOURCE29 INTMASK_VICSOURCE29 +#define FIQMASK_VICSOURCE30 INTMASK_VICSOURCE30 +#define FIQMASK_VICSOURCE31 INTMASK_VICSOURCE31 + +/* + * Secondary interrupt controller + */ +#define IRQ_SIC_START 32 +#define IRQ_SIC_MMCI0B (IRQ_SIC_START + SIC_INT_MMCI0B) +#define IRQ_SIC_MMCI1B (IRQ_SIC_START + SIC_INT_MMCI1B) +#define IRQ_SIC_KMI0 (IRQ_SIC_START + SIC_INT_KMI0) +#define IRQ_SIC_KMI1 (IRQ_SIC_START + SIC_INT_KMI1) +#define IRQ_SIC_SCI3 (IRQ_SIC_START + SIC_INT_SCI3) +#define IRQ_SIC_UART3 (IRQ_SIC_START + SIC_INT_UART3) +#define IRQ_SIC_CLCD (IRQ_SIC_START + SIC_INT_CLCD) +#define IRQ_SIC_TOUCH (IRQ_SIC_START + SIC_INT_TOUCH) +#define IRQ_SIC_KEYPAD (IRQ_SIC_START + SIC_INT_KEYPAD) +#define IRQ_SIC_DoC (IRQ_SIC_START + SIC_INT_DoC) +#define IRQ_SIC_MMCI0A (IRQ_SIC_START + SIC_INT_MMCI0A) +#define IRQ_SIC_MMCI1A (IRQ_SIC_START + SIC_INT_MMCI1A) +#define IRQ_SIC_AACI (IRQ_SIC_START + SIC_INT_AACI) +#define IRQ_SIC_ETH (IRQ_SIC_START + SIC_INT_ETH) +#define IRQ_SIC_USB (IRQ_SIC_START + SIC_INT_USB) +#define IRQ_SIC_PCI0 (IRQ_SIC_START + SIC_INT_PCI0) +#define IRQ_SIC_PCI1 (IRQ_SIC_START + SIC_INT_PCI1) +#define IRQ_SIC_PCI2 (IRQ_SIC_START + SIC_INT_PCI2) +#define IRQ_SIC_PCI3 (IRQ_SIC_START + SIC_INT_PCI3) +#define IRQ_SIC_END 63 + +#define SIC_IRQMASK_MMCI0B SIC_INTMASK_MMCI0B +#define SIC_IRQMASK_MMCI1B SIC_INTMASK_MMCI1B +#define SIC_IRQMASK_KMI0 SIC_INTMASK_KMI0 +#define SIC_IRQMASK_KMI1 SIC_INTMASK_KMI1 +#define SIC_IRQMASK_SCI3 SIC_INTMASK_SCI3 +#define SIC_IRQMASK_UART3 SIC_INTMASK_UART3 +#define SIC_IRQMASK_CLCD SIC_INTMASK_CLCD +#define SIC_IRQMASK_TOUCH SIC_INTMASK_TOUCH +#define SIC_IRQMASK_KEYPAD SIC_INTMASK_KEYPAD +#define SIC_IRQMASK_DoC SIC_INTMASK_DoC +#define SIC_IRQMASK_MMCI0A SIC_INTMASK_MMCI0A +#define SIC_IRQMASK_MMCI1A SIC_INTMASK_MMCI1A +#define SIC_IRQMASK_AACI SIC_INTMASK_AACI +#define SIC_IRQMASK_ETH SIC_INTMASK_ETH +#define SIC_IRQMASK_USB SIC_INTMASK_USB +#define SIC_IRQMASK_PCI0 SIC_INTMASK_PCI0 +#define SIC_IRQMASK_PCI1 SIC_INTMASK_PCI1 +#define SIC_IRQMASK_PCI2 SIC_INTMASK_PCI2 +#define SIC_IRQMASK_PCI3 SIC_INTMASK_PCI3 + +#define NR_IRQS 64 diff -uNr xen-unstable.hg/xen/include/asm-arm/arch-versatile/platform.h xen-arm-ver/xen/include/asm-arm/arch-versatile/platform.h --- xen-unstable.hg/xen/include/asm-arm/arch-versatile/platform.h 1969-12-31 19:00:00.000000000 -0500 +++ xen-arm-ver/xen/include/asm-arm/arch-versatile/platform.h 2008-11-10 11:06:08.000000000 -0500 @@ -0,0 +1,510 @@ +/* + * arch/arm/mach-versatile/include/mach/platform.h + * + * Copyright (c) ARM Limited 2003. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __address_h +#define __address_h 1 + +/* + * Memory definitions + */ +#define VERSATILE_BOOT_ROM_LO 0x30000000 /* DoC Base (64Mb)...*/ +#define VERSATILE_BOOT_ROM_HI 0x30000000 +#define VERSATILE_BOOT_ROM_BASE VERSATILE_BOOT_ROM_HI /* Normal position */ +#define VERSATILE_BOOT_ROM_SIZE SZ_64M + +#define VERSATILE_SSRAM_BASE /* VERSATILE_SSMC_BASE ? */ +#define VERSATILE_SSRAM_SIZE SZ_2M + +#define VERSATILE_FLASH_BASE 0x34000000 +#define VERSATILE_FLASH_SIZE SZ_64M + +/* + * SDRAM + */ +#define VERSATILE_SDRAM_BASE 0x04000000 + +/* + * Logic expansion modules + * + */ + + +/* ------------------------------------------------------------------------ + * Versatile Registers + * ------------------------------------------------------------------------ + * + */ +#define VERSATILE_SYS_ID_OFFSET 0x00 +#define VERSATILE_SYS_SW_OFFSET 0x04 +#define VERSATILE_SYS_LED_OFFSET 0x08 +#define VERSATILE_SYS_OSC0_OFFSET 0x0C + +#if defined(CONFIG_ARCH_VERSATILE_PB) +#define VERSATILE_SYS_OSC1_OFFSET 0x10 +#define VERSATILE_SYS_OSC2_OFFSET 0x14 +#define VERSATILE_SYS_OSC3_OFFSET 0x18 +#define VERSATILE_SYS_OSC4_OFFSET 0x1C +#elif defined(CONFIG_MACH_VERSATILE_AB) +#define VERSATILE_SYS_OSC1_OFFSET 0x1C +#endif + +#define VERSATILE_SYS_OSCCLCD_OFFSET 0x1c + +#define VERSATILE_SYS_LOCK_OFFSET 0x20 +#define VERSATILE_SYS_100HZ_OFFSET 0x24 +#define VERSATILE_SYS_CFGDATA1_OFFSET 0x28 +#define VERSATILE_SYS_CFGDATA2_OFFSET 0x2C +#define VERSATILE_SYS_FLAGS_OFFSET 0x30 +#define VERSATILE_SYS_FLAGSSET_OFFSET 0x30 +#define VERSATILE_SYS_FLAGSCLR_OFFSET 0x34 +#define VERSATILE_SYS_NVFLAGS_OFFSET 0x38 +#define VERSATILE_SYS_NVFLAGSSET_OFFSET 0x38 +#define VERSATILE_SYS_NVFLAGSCLR_OFFSET 0x3C +#define VERSATILE_SYS_RESETCTL_OFFSET 0x40 +#define VERSATILE_SYS_PCICTL_OFFSET 0x44 +#define VERSATILE_SYS_MCI_OFFSET 0x48 +#define VERSATILE_SYS_FLASH_OFFSET 0x4C +#define VERSATILE_SYS_CLCD_OFFSET 0x50 +#define VERSATILE_SYS_CLCDSER_OFFSET 0x54 +#define VERSATILE_SYS_BOOTCS_OFFSET 0x58 +#define VERSATILE_SYS_24MHz_OFFSET 0x5C +#define VERSATILE_SYS_MISC_OFFSET 0x60 +#define VERSATILE_SYS_TEST_OSC0_OFFSET 0x80 +#define VERSATILE_SYS_TEST_OSC1_OFFSET 0x84 +#define VERSATILE_SYS_TEST_OSC2_OFFSET 0x88 +#define VERSATILE_SYS_TEST_OSC3_OFFSET 0x8C +#define VERSATILE_SYS_TEST_OSC4_OFFSET 0x90 + +#define VERSATILE_SYS_BASE 0x10000000 +#define VERSATILE_SYS_ID (VERSATILE_SYS_BASE + VERSATILE_SYS_ID_OFFSET) +#define VERSATILE_SYS_SW (VERSATILE_SYS_BASE + VERSATILE_SYS_SW_OFFSET) +#define VERSATILE_SYS_LED (VERSATILE_SYS_BASE + VERSATILE_SYS_LED_OFFSET) +#define VERSATILE_SYS_OSC0 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC0_OFFSET) +#define VERSATILE_SYS_OSC1 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC1_OFFSET) + +#if defined(CONFIG_ARCH_VERSATILE_PB) +#define VERSATILE_SYS_OSC2 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC2_OFFSET) +#define VERSATILE_SYS_OSC3 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC3_OFFSET) +#define VERSATILE_SYS_OSC4 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC4_OFFSET) +#endif + +#define VERSATILE_SYS_LOCK (VERSATILE_SYS_BASE + VERSATILE_SYS_LOCK_OFFSET) +#define VERSATILE_SYS_100HZ (VERSATILE_SYS_BASE + VERSATILE_SYS_100HZ_OFFSET) +#define VERSATILE_SYS_CFGDATA1 (VERSATILE_SYS_BASE + VERSATILE_SYS_CFGDATA1_OFFSET) +#define VERSATILE_SYS_CFGDATA2 (VERSATILE_SYS_BASE + VERSATILE_SYS_CFGDATA2_OFFSET) +#define VERSATILE_SYS_FLAGS (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGS_OFFSET) +#define VERSATILE_SYS_FLAGSSET (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGSSET_OFFSET) +#define VERSATILE_SYS_FLAGSCLR (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGSCLR_OFFSET) +#define VERSATILE_SYS_NVFLAGS (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGS_OFFSET) +#define VERSATILE_SYS_NVFLAGSSET (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGSSET_OFFSET) +#define VERSATILE_SYS_NVFLAGSCLR (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGSCLR_OFFSET) +#define VERSATILE_SYS_RESETCTL (VERSATILE_SYS_BASE + VERSATILE_SYS_RESETCTL_OFFSET) +#define VERSATILE_SYS_PCICTL (VERSATILE_SYS_BASE + VERSATILE_SYS_PCICTL_OFFSET) +#define VERSATILE_SYS_MCI (VERSATILE_SYS_BASE + VERSATILE_SYS_MCI_OFFSET) +#define VERSATILE_SYS_FLASH (VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET) +#define VERSATILE_SYS_CLCD (VERSATILE_SYS_BASE + VERSATILE_SYS_CLCD_OFFSET) +#define VERSATILE_SYS_CLCDSER (VERSATILE_SYS_BASE + VERSATILE_SYS_CLCDSER_OFFSET) +#define VERSATILE_SYS_BOOTCS (VERSATILE_SYS_BASE + VERSATILE_SYS_BOOTCS_OFFSET) +#define VERSATILE_SYS_24MHz (VERSATILE_SYS_BASE + VERSATILE_SYS_24MHz_OFFSET) +#define VERSATILE_SYS_MISC (VERSATILE_SYS_BASE + VERSATILE_SYS_MISC_OFFSET) +#define VERSATILE_SYS_TEST_OSC0 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC0_OFFSET) +#define VERSATILE_SYS_TEST_OSC1 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC1_OFFSET) +#define VERSATILE_SYS_TEST_OSC2 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC2_OFFSET) +#define VERSATILE_SYS_TEST_OSC3 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC3_OFFSET) +#define VERSATILE_SYS_TEST_OSC4 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC4_OFFSET) + +/* + * Values for VERSATILE_SYS_RESET_CTRL + */ +#define VERSATILE_SYS_CTRL_RESET_CONFIGCLR 0x01 +#define VERSATILE_SYS_CTRL_RESET_CONFIGINIT 0x02 +#define VERSATILE_SYS_CTRL_RESET_DLLRESET 0x03 +#define VERSATILE_SYS_CTRL_RESET_PLLRESET 0x04 +#define VERSATILE_SYS_CTRL_RESET_POR 0x05 +#define VERSATILE_SYS_CTRL_RESET_DoC 0x06 + +#define VERSATILE_SYS_CTRL_LED (1 << 0) + + +/* ------------------------------------------------------------------------ + * Versatile control registers + * ------------------------------------------------------------------------ + */ + +/* + * VERSATILE_IDFIELD + * + * 31:24 = manufacturer (0x41 = ARM) + * 23:16 = architecture (0x08 = AHB system bus, ASB processor bus) + * 15:12 = FPGA (0x3 = XVC600 or XVC600E) + * 11:4 = build value + * 3:0 = revision number (0x1 = rev B (AHB)) + */ + +/* + * VERSATILE_SYS_LOCK + * control access to SYS_OSCx, SYS_CFGDATAx, SYS_RESETCTL, + * SYS_CLD, SYS_BOOTCS + */ +#define VERSATILE_SYS_LOCK_LOCKED (1 << 16) +#define VERSATILE_SYS_LOCKVAL_MASK 0xFFFF /* write 0xA05F to enable write access */ + +/* + * VERSATILE_SYS_FLASH + */ +#define VERSATILE_FLASHPROG_FLVPPEN (1 << 0) /* Enable writing to flash */ + +/* + * VERSATILE_INTREG + * - used to acknowledge and control MMCI and UART interrupts + */ +#define VERSATILE_INTREG_WPROT 0x00 /* MMC protection status (no interrupt generated) */ +#define VERSATILE_INTREG_RI0 0x01 /* Ring indicator UART0 is asserted, */ +#define VERSATILE_INTREG_CARDIN 0x08 /* MMCI card in detect */ + /* write 1 to acknowledge and clear */ +#define VERSATILE_INTREG_RI1 0x02 /* Ring indicator UART1 is asserted, */ +#define VERSATILE_INTREG_CARDINSERT 0x03 /* Signal insertion of MMC card */ + +/* + * VERSATILE peripheral addresses + */ +#define VERSATILE_PCI_CORE_BASE 0x10001000 /* PCI core control */ +#define VERSATILE_I2C_BASE 0x10002000 /* I2C control */ +#define VERSATILE_SIC_BASE 0x10003000 /* Secondary interrupt controller */ +#define VERSATILE_AACI_BASE 0x10004000 /* Audio */ +#define VERSATILE_MMCI0_BASE 0x10005000 /* MMC interface */ +#define VERSATILE_KMI0_BASE 0x10006000 /* KMI interface */ +#define VERSATILE_KMI1_BASE 0x10007000 /* KMI 2nd interface */ +#define VERSATILE_CHAR_LCD_BASE 0x10008000 /* Character LCD */ +#define VERSATILE_UART3_BASE 0x10009000 /* UART 3 */ +#define VERSATILE_SCI1_BASE 0x1000A000 +#define VERSATILE_MMCI1_BASE 0x1000B000 /* MMC Interface */ + /* 0x1000C000 - 0x1000CFFF = reserved */ +#define VERSATILE_ETH_BASE 0x10010000 /* Ethernet */ +#define VERSATILE_USB_BASE 0x10020000 /* USB */ + /* 0x10030000 - 0x100FFFFF = reserved */ +#define VERSATILE_SMC_BASE 0x10100000 /* SMC */ +#define VERSATILE_MPMC_BASE 0x10110000 /* MPMC */ +#define VERSATILE_CLCD_BASE 0x10120000 /* CLCD */ +#define VERSATILE_DMAC_BASE 0x10130000 /* DMA controller */ +#define VERSATILE_VIC_BASE 0x10140000 /* Vectored interrupt controller */ +#define VERSATILE_PERIPH_BASE 0x10150000 /* off-chip peripherals alias from */ + /* 0x10000000 - 0x100FFFFF */ +#define VERSATILE_AHBM_BASE 0x101D0000 /* AHB monitor */ +#define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */ +#define VERSATILE_WATCHDOG_BASE 0x101E1000 /* Watchdog */ +#define VERSATILE_TIMER0_1_BASE 0x101E2000 /* Timer 0 and 1 */ +#define VERSATILE_TIMER2_3_BASE 0x101E3000 /* Timer 2 and 3 */ +#define VERSATILE_GPIO0_BASE 0x101E4000 /* GPIO port 0 */ +#define VERSATILE_GPIO1_BASE 0x101E5000 /* GPIO port 1 */ +#define VERSATILE_GPIO2_BASE 0x101E6000 /* GPIO port 2 */ +#define VERSATILE_GPIO3_BASE 0x101E7000 /* GPIO port 3 */ +#define VERSATILE_RTC_BASE 0x101E8000 /* Real Time Clock */ + /* 0x101E9000 - reserved */ +#define VERSATILE_SCI_BASE 0x101F0000 /* Smart card controller */ +#define VERSATILE_UART0_BASE 0x101F1000 /* Uart 0 */ +#define VERSATILE_UART1_BASE 0x101F2000 /* Uart 1 */ +#define VERSATILE_UART2_BASE 0x101F3000 /* Uart 2 */ +#define VERSATILE_SSP_BASE 0x101F4000 /* Synchronous Serial Port */ + +#define VERSATILE_SSMC_BASE 0x20000000 /* SSMC */ +#define VERSATILE_IB2_BASE 0x24000000 /* IB2 module */ +#define VERSATILE_MBX_BASE 0x40000000 /* MBX */ + +/* PCI space */ +#define VERSATILE_PCI_BASE 0x41000000 /* PCI Interface */ +#define VERSATILE_PCI_CFG_BASE 0x42000000 +#define VERSATILE_PCI_MEM_BASE0 0x44000000 +#define VERSATILE_PCI_MEM_BASE1 0x50000000 +#define VERSATILE_PCI_MEM_BASE2 0x60000000 +/* Sizes of above maps */ +#define VERSATILE_PCI_BASE_SIZE 0x01000000 +#define VERSATILE_PCI_CFG_BASE_SIZE 0x02000000 +#define VERSATILE_PCI_MEM_BASE0_SIZE 0x0c000000 /* 32Mb */ +#define VERSATILE_PCI_MEM_BASE1_SIZE 0x10000000 /* 256Mb */ +#define VERSATILE_PCI_MEM_BASE2_SIZE 0x10000000 /* 256Mb */ + +#define VERSATILE_SDRAM67_BASE 0x70000000 /* SDRAM banks 6 and 7 */ +#define VERSATILE_LT_BASE 0x80000000 /* Logic Tile expansion */ + +/* + * Disk on Chip + */ +#define VERSATILE_DOC_BASE 0x2C000000 +#define VERSATILE_DOC_SIZE (16 << 20) +#define VERSATILE_DOC_PAGE_SIZE 512 +#define VERSATILE_DOC_TOTAL_PAGES (DOC_SIZE / PAGE_SIZE) + +#define ERASE_UNIT_PAGES 32 +#define START_PAGE 0x80 + +/* + * LED settings, bits [7:0] + */ +#define VERSATILE_SYS_LED0 (1 << 0) +#define VERSATILE_SYS_LED1 (1 << 1) +#define VERSATILE_SYS_LED2 (1 << 2) +#define VERSATILE_SYS_LED3 (1 << 3) +#define VERSATILE_SYS_LED4 (1 << 4) +#define VERSATILE_SYS_LED5 (1 << 5) +#define VERSATILE_SYS_LED6 (1 << 6) +#define VERSATILE_SYS_LED7 (1 << 7) + +#define ALL_LEDS 0xFF + +#define LED_BANK VERSATILE_SYS_LED + +/* + * Control registers + */ +#define VERSATILE_IDFIELD_OFFSET 0x0 /* Versatile build information */ +#define VERSATILE_FLASHPROG_OFFSET 0x4 /* Flash devices */ +#define VERSATILE_INTREG_OFFSET 0x8 /* Interrupt control */ +#define VERSATILE_DECODE_OFFSET 0xC /* Fitted logic modules */ + + +/* ------------------------------------------------------------------------ + * Versatile Interrupt Controller - control registers + * ------------------------------------------------------------------------ + * + * Offsets from interrupt controller base + * + * System Controller interrupt controller base is + * + * VERSATILE_IC_BASE + * + * Core Module interrupt controller base is + * + * VERSATILE_SYS_IC + * + */ +/* VIC definitions in include/asm-arm/hardware/vic.h */ + +#define SIC_IRQ_STATUS 0 +#define SIC_IRQ_RAW_STATUS 0x04 +#define SIC_IRQ_ENABLE 0x08 +#define SIC_IRQ_ENABLE_SET 0x08 +#define SIC_IRQ_ENABLE_CLEAR 0x0C +#define SIC_INT_SOFT_SET 0x10 +#define SIC_INT_SOFT_CLEAR 0x14 +#define SIC_INT_PIC_ENABLE 0x20 /* read status of pass through mask */ +#define SIC_INT_PIC_ENABLES 0x20 /* set interrupt pass through bits */ +#define SIC_INT_PIC_ENABLEC 0x24 /* Clear interrupt pass through bits */ + +/* ------------------------------------------------------------------------ + * Interrupts - bit assignment (primary) + * ------------------------------------------------------------------------ + */ + +#define INT_WDOGINT 0 /* Watchdog timer */ +#define INT_SOFTINT 1 /* Software interrupt */ +#define INT_COMMRx 2 /* Debug Comm Rx interrupt */ +#define INT_COMMTx 3 /* Debug Comm Tx interrupt */ +#define INT_TIMERINT0_1 4 /* Timer 0 and 1 */ +#define INT_TIMERINT2_3 5 /* Timer 2 and 3 */ +#define INT_GPIOINT0 6 /* GPIO 0 */ +#define INT_GPIOINT1 7 /* GPIO 1 */ +#define INT_GPIOINT2 8 /* GPIO 2 */ +#define INT_GPIOINT3 9 /* GPIO 3 */ +#define INT_RTCINT 10 /* Real Time Clock */ +#define INT_SSPINT 11 /* Synchronous Serial Port */ +#define INT_UARTINT0 12 /* UART 0 on development chip */ +#define INT_UARTINT1 13 /* UART 1 on development chip */ +#define INT_UARTINT2 14 /* UART 2 on development chip */ +#define INT_SCIINT 15 /* Smart Card Interface */ +#define INT_CLCDINT 16 /* CLCD controller */ +#define INT_DMAINT 17 /* DMA controller */ +#define INT_PWRFAILINT 18 /* Power failure */ +#define INT_MBXINT 19 /* Graphics processor */ +#define INT_GNDINT 20 /* Reserved */ + /* External interrupt signals from logic tiles or secondary controller */ +#define INT_VICSOURCE21 21 /* Disk on Chip */ +#define INT_VICSOURCE22 22 /* MCI0A */ +#define INT_VICSOURCE23 23 /* MCI1A */ +#define INT_VICSOURCE24 24 /* AACI */ +#define INT_VICSOURCE25 25 /* Ethernet */ +#define INT_VICSOURCE26 26 /* USB */ +#define INT_VICSOURCE27 27 /* PCI 0 */ +#define INT_VICSOURCE28 28 /* PCI 1 */ +#define INT_VICSOURCE29 29 /* PCI 2 */ +#define INT_VICSOURCE30 30 /* PCI 3 */ +#define INT_VICSOURCE31 31 /* SIC source */ + +/* + * Interrupt bit positions + * + */ +#define INTMASK_WDOGINT (1 << INT_WDOGINT) +#define INTMASK_SOFTINT (1 << INT_SOFTINT) +#define INTMASK_COMMRx (1 << INT_COMMRx) +#define INTMASK_COMMTx (1 << INT_COMMTx) +#define INTMASK_TIMERINT0_1 (1 << INT_TIMERINT0_1) +#define INTMASK_TIMERINT2_3 (1 << INT_TIMERINT2_3) +#define INTMASK_GPIOINT0 (1 << INT_GPIOINT0) +#define INTMASK_GPIOINT1 (1 << INT_GPIOINT1) +#define INTMASK_GPIOINT2 (1 << INT_GPIOINT2) +#define INTMASK_GPIOINT3 (1 << INT_GPIOINT3) +#define INTMASK_RTCINT (1 << INT_RTCINT) +#define INTMASK_SSPINT (1 << INT_SSPINT) +#define INTMASK_UARTINT0 (1 << INT_UARTINT0) +#define INTMASK_UARTINT1 (1 << INT_UARTINT1) +#define INTMASK_UARTINT2 (1 << INT_UARTINT2) +#define INTMASK_SCIINT (1 << INT_SCIINT) +#define INTMASK_CLCDINT (1 << INT_CLCDINT) +#define INTMASK_DMAINT (1 << INT_DMAINT) +#define INTMASK_PWRFAILINT (1 << INT_PWRFAILINT) +#define INTMASK_MBXINT (1 << INT_MBXINT) +#define INTMASK_GNDINT (1 << INT_GNDINT) +#define INTMASK_VICSOURCE21 (1 << INT_VICSOURCE21) +#define INTMASK_VICSOURCE22 (1 << INT_VICSOURCE22) +#define INTMASK_VICSOURCE23 (1 << INT_VICSOURCE23) +#define INTMASK_VICSOURCE24 (1 << INT_VICSOURCE24) +#define INTMASK_VICSOURCE25 (1 << INT_VICSOURCE25) +#define INTMASK_VICSOURCE26 (1 << INT_VICSOURCE26) +#define INTMASK_VICSOURCE27 (1 << INT_VICSOURCE27) +#define INTMASK_VICSOURCE28 (1 << INT_VICSOURCE28) +#define INTMASK_VICSOURCE29 (1 << INT_VICSOURCE29) +#define INTMASK_VICSOURCE30 (1 << INT_VICSOURCE30) +#define INTMASK_VICSOURCE31 (1 << INT_VICSOURCE31) + + +#define VERSATILE_SC_VALID_INT 0x003FFFFF + +#define MAXIRQNUM 31 +#define MAXFIQNUM 31 +#define MAXSWINUM 31 + +/* ------------------------------------------------------------------------ + * Interrupts - bit assignment (secondary) + * ------------------------------------------------------------------------ + */ +#define SIC_INT_MMCI0B 1 /* Multimedia Card 0B */ +#define SIC_INT_MMCI1B 2 /* Multimedia Card 1B */ +#define SIC_INT_KMI0 3 /* Keyboard/Mouse port 0 */ +#define SIC_INT_KMI1 4 /* Keyboard/Mouse port 1 */ +#define SIC_INT_SCI3 5 /* Smart Card interface */ +#define SIC_INT_UART3 6 /* UART 3 empty or data available */ +#define SIC_INT_CLCD 7 /* Character LCD */ +#define SIC_INT_TOUCH 8 /* Touchscreen */ +#define SIC_INT_KEYPAD 9 /* Key pressed on display keypad */ + /* 10:20 - reserved */ +#define SIC_INT_DoC 21 /* Disk on Chip memory controller */ +#define SIC_INT_MMCI0A 22 /* MMC 0A */ +#define SIC_INT_MMCI1A 23 /* MMC 1A */ +#define SIC_INT_AACI 24 /* Audio Codec */ +#define SIC_INT_ETH 25 /* Ethernet controller */ +#define SIC_INT_USB 26 /* USB controller */ +#define SIC_INT_PCI0 27 +#define SIC_INT_PCI1 28 +#define SIC_INT_PCI2 29 +#define SIC_INT_PCI3 30 + + +#define SIC_INTMASK_MMCI0B (1 << SIC_INT_MMCI0B) +#define SIC_INTMASK_MMCI1B (1 << SIC_INT_MMCI1B) +#define SIC_INTMASK_KMI0 (1 << SIC_INT_KMI0) +#define SIC_INTMASK_KMI1 (1 << SIC_INT_KMI1) +#define SIC_INTMASK_SCI3 (1 << SIC_INT_SCI3) +#define SIC_INTMASK_UART3 (1 << SIC_INT_UART3) +#define SIC_INTMASK_CLCD (1 << SIC_INT_CLCD) +#define SIC_INTMASK_TOUCH (1 << SIC_INT_TOUCH) +#define SIC_INTMASK_KEYPAD (1 << SIC_INT_KEYPAD) +#define SIC_INTMASK_DoC (1 << SIC_INT_DoC) +#define SIC_INTMASK_MMCI0A (1 << SIC_INT_MMCI0A) +#define SIC_INTMASK_MMCI1A (1 << SIC_INT_MMCI1A) +#define SIC_INTMASK_AACI (1 << SIC_INT_AACI) +#define SIC_INTMASK_ETH (1 << SIC_INT_ETH) +#define SIC_INTMASK_USB (1 << SIC_INT_USB) +#define SIC_INTMASK_PCI0 (1 << SIC_INT_PCI0) +#define SIC_INTMASK_PCI1 (1 << SIC_INT_PCI1) +#define SIC_INTMASK_PCI2 (1 << SIC_INT_PCI2) +#define SIC_INTMASK_PCI3 (1 << SIC_INT_PCI3) +/* + * Application Flash + * + */ +#define FLASH_BASE VERSATILE_FLASH_BASE +#define FLASH_SIZE VERSATILE_FLASH_SIZE +#define FLASH_END (FLASH_BASE + FLASH_SIZE - 1) +#define FLASH_BLOCK_SIZE SZ_128K + +/* + * Boot Flash + * + */ +#define EPROM_BASE VERSATILE_BOOT_ROM_HI +#define EPROM_SIZE VERSATILE_BOOT_ROM_SIZE +#define EPROM_END (EPROM_BASE + EPROM_SIZE - 1) + +/* + * Clean base - dummy + * + */ +#define CLEAN_BASE EPROM_BASE + +/* + * System controller bit assignment + */ +#define VERSATILE_REFCLK 0 +#define VERSATILE_TIMCLK 1 + +#define VERSATILE_TIMER1_EnSel 15 +#define VERSATILE_TIMER2_EnSel 17 +#define VERSATILE_TIMER3_EnSel 19 +#define VERSATILE_TIMER4_EnSel 21 + + +#define MAX_TIMER 2 +#define MAX_PERIOD 699050 +#define TICKS_PER_uSEC 1 + +/* + * These are useconds NOT ticks. + * + */ +#define mSEC_1 1000 +#define mSEC_5 (mSEC_1 * 5) +#define mSEC_10 (mSEC_1 * 10) +#define mSEC_25 (mSEC_1 * 25) +#define SEC_1 (mSEC_1 * 1000) + +#define VERSATILE_CSR_BASE 0x10000000 +#define VERSATILE_CSR_SIZE 0x10000000 + +#ifdef CONFIG_MACH_VERSATILE_AB +/* + * IB2 Versatile/AB expansion board definitions + */ +#define VERSATILE_IB2_CAMERA_BANK VERSATILE_IB2_BASE +#define VERSATILE_IB2_KBD_DATAREG (VERSATILE_IB2_BASE + 0x01000000) + +/* VICINTSOURCE27 */ +#define VERSATILE_IB2_INT_BASE (VERSATILE_IB2_BASE + 0x02000000) +#define VERSATILE_IB2_IER (VERSATILE_IB2_INT_BASE + 0) +#define VERSATILE_IB2_ISR (VERSATILE_IB2_INT_BASE + 4) + +#define VERSATILE_IB2_CTL_BASE (VERSATILE_IB2_BASE + 0x03000000) +#define VERSATILE_IB2_CTRL (VERSATILE_IB2_CTL_BASE + 0) +#define VERSATILE_IB2_STAT (VERSATILE_IB2_CTL_BASE + 4) +#endif + +#endif + +/* END */ diff -uNr xen-unstable.hg/xen/include/asm-arm/arch-versatile/regs.h xen-arm-ver/xen/include/asm-arm/arch-versatile/regs.h --- xen-unstable.hg/xen/include/asm-arm/arch-versatile/regs.h 1969-12-31 19:00:00.000000000 -0500 +++ xen-arm-ver/xen/include/asm-arm/arch-versatile/regs.h 2008-10-24 16:58:17.000000000 -0400 @@ -0,0 +1,4 @@ +#ifndef __VERSATILEPB_REGS_H__ +#define __VERSATILEPB_REGS_H__ + +#endif diff -uNr xen-unstable.hg/xen/include/asm-arm/arch-versatile/serial_pl011.h xen-arm-ver/xen/include/asm-arm/arch-versatile/serial_pl011.h --- xen-unstable.hg/xen/include/asm-arm/arch-versatile/serial_pl011.h 1969-12-31 19:00:00.000000000 -0500 +++ xen-arm-ver/xen/include/asm-arm/arch-versatile/serial_pl011.h 2008-11-14 11:47:07.000000000 -0500 @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2003, 2004 + * ARM Ltd. + * Philippe Robin, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * ARM PrimeCell UART's (PL010 & PL011) + * ------------------------------------ + * + * Definitions common to both PL010 & PL011 + * + */ +#define UART_PL01x_DR 0x00 /* Data read or written from the interface. */ +#define UART_PL01x_RSR 0x04 /* Receive status register (Read). */ +#define UART_PL01x_ECR 0x04 /* Error clear register (Write). */ +#define UART_PL01x_FR 0x18 /* Flag register (Read only). */ + +#define UART_PL01x_RSR_OE 0x08 +#define UART_PL01x_RSR_BE 0x04 +#define UART_PL01x_RSR_PE 0x02 +#define UART_PL01x_RSR_FE 0x01 + +#define UART_PL01x_FR_TXFE 0x80 +#define UART_PL01x_FR_RXFF 0x40 +#define UART_PL01x_FR_TXFF 0x20 +#define UART_PL01x_FR_RXFE 0x10 +#define UART_PL01x_FR_BUSY 0x08 +#define UART_PL01x_FR_TMSK (UART_PL01x_FR_TXFF + UART_PL01x_FR_BUSY) + +/* + * PL010 definitions + * + */ +#define UART_PL010_LCRH 0x08 /* Line control register, high byte. */ +#define UART_PL010_LCRM 0x0C /* Line control register, middle byte. */ +#define UART_PL010_LCRL 0x10 /* Line control register, low byte. */ +#define UART_PL010_CR 0x14 /* Control register. */ +#define UART_PL010_IIR 0x1C /* Interrupt indentification register (Read). */ +#define UART_PL010_ICR 0x1C /* Interrupt clear register (Write). */ +#define UART_PL010_ILPR 0x20 /* IrDA low power counter register. */ + +#define UART_PL010_CR_LPE (1 << 7) +#define UART_PL010_CR_RTIE (1 << 6) +#define UART_PL010_CR_TIE (1 << 5) +#define UART_PL010_CR_RIE (1 << 4) +#define UART_PL010_CR_MSIE (1 << 3) +#define UART_PL010_CR_IIRLP (1 << 2) +#define UART_PL010_CR_SIREN (1 << 1) +#define UART_PL010_CR_UARTEN (1 << 0) + +#define UART_PL010_LCRH_WLEN_8 (3 << 5) +#define UART_PL010_LCRH_WLEN_7 (2 << 5) +#define UART_PL010_LCRH_WLEN_6 (1 << 5) +#define UART_PL010_LCRH_WLEN_5 (0 << 5) +#define UART_PL010_LCRH_FEN (1 << 4) +#define UART_PL010_LCRH_STP2 (1 << 3) +#define UART_PL010_LCRH_EPS (1 << 2) +#define UART_PL010_LCRH_PEN (1 << 1) +#define UART_PL010_LCRH_BRK (1 << 0) + + +#define UART_PL010_BAUD_460800 1 +#define UART_PL010_BAUD_230400 3 +#define UART_PL010_BAUD_115200 7 +#define UART_PL010_BAUD_57600 15 +#define UART_PL010_BAUD_38400 23 +#define UART_PL010_BAUD_19200 47 +#define UART_PL010_BAUD_14400 63 +#define UART_PL010_BAUD_9600 95 +#define UART_PL010_BAUD_4800 191 +#define UART_PL010_BAUD_2400 383 +#define UART_PL010_BAUD_1200 767 +/* + * PL011 definitions + * + */ +#define UART_PL011_IBRD 0x24 +#define UART_PL011_FBRD 0x28 +#define UART_PL011_LCRH 0x2C +#define UART_PL011_CR 0x30 +#define UART_PL011_IMSC 0x38 +#define UART_PL011_PERIPH_ID0 0xFE0 + +#define UART_PL011_LCRH_SPS (1 << 7) +#define UART_PL011_LCRH_WLEN_8 (3 << 5) +#define UART_PL011_LCRH_WLEN_7 (2 << 5) +#define UART_PL011_LCRH_WLEN_6 (1 << 5) +#define UART_PL011_LCRH_WLEN_5 (0 << 5) +#define UART_PL011_LCRH_FEN (1 << 4) +#define UART_PL011_LCRH_STP2 (1 << 3) +#define UART_PL011_LCRH_EPS (1 << 2) +#define UART_PL011_LCRH_PEN (1 << 1) +#define UART_PL011_LCRH_BRK (1 << 0) + +#define UART_PL011_CR_CTSEN (1 << 15) +#define UART_PL011_CR_RTSEN (1 << 14) +#define UART_PL011_CR_OUT2 (1 << 13) +#define UART_PL011_CR_OUT1 (1 << 12) +#define UART_PL011_CR_RTS (1 << 11) +#define UART_PL011_CR_DTR (1 << 10) +#define UART_PL011_CR_RXE (1 << 9) +#define UART_PL011_CR_TXE (1 << 8) +#define UART_PL011_CR_LPE (1 << 7) +#define UART_PL011_CR_IIRLP (1 << 2) +#define UART_PL011_CR_SIREN (1 << 1) +#define UART_PL011_CR_UARTEN (1 << 0) + +#define UART_PL011_IMSC_OEIM (1 << 10) +#define UART_PL011_IMSC_BEIM (1 << 9) +#define UART_PL011_IMSC_PEIM (1 << 8) +#define UART_PL011_IMSC_FEIM (1 << 7) +#define UART_PL011_IMSC_RTIM (1 << 6) +#define UART_PL011_IMSC_TXIM (1 << 5) +#define UART_PL011_IMSC_RXIM (1 << 4) +#define UART_PL011_IMSC_DSRMIM (1 << 3) +#define UART_PL011_IMSC_DCDMIM (1 << 2) +#define UART_PL011_IMSC_CTSMIM (1 << 1) +#define UART_PL011_IMSC_RIMIM (1 << 0) diff -uNr xen-unstable.hg/xen/include/asm-arm/arch-versatile/system.h xen-arm-ver/xen/include/asm-arm/arch-versatile/system.h --- xen-unstable.hg/xen/include/asm-arm/arch-versatile/system.h 1969-12-31 19:00:00.000000000 -0500 +++ xen-arm-ver/xen/include/asm-arm/arch-versatile/system.h 2008-10-24 15:01:04.000000000 -0400 @@ -0,0 +1,49 @@ +/* + * arch/arm/mach-versatile/include/mach/system.h + * + * Copyright (C) 2003 ARM Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H + +#include +#include +#include + +static inline void arch_idle(void) +{ + /* + * This should do all the clock switching + * and wait for interrupt tricks + */ + cpu_do_idle(); +} + +static inline void arch_reset(char mode) +{ + u32 val; + + val = __raw_readl(IO_ADDRESS(VERSATILE_SYS_RESETCTL)) & ~0x7; + val |= 0x105; + + __raw_writel(0xa05f, IO_ADDRESS(VERSATILE_SYS_LOCK)); + __raw_writel(val, IO_ADDRESS(VERSATILE_SYS_RESETCTL)); + __raw_writel(0, IO_ADDRESS(VERSATILE_SYS_LOCK)); +} + +#endif diff -uNr xen-unstable.hg/xen/include/asm-arm/arch-versatile/timer.h xen-arm-ver/xen/include/asm-arm/arch-versatile/timer.h --- xen-unstable.hg/xen/include/asm-arm/arch-versatile/timer.h 1969-12-31 19:00:00.000000000 -0500 +++ xen-arm-ver/xen/include/asm-arm/arch-versatile/timer.h 2008-10-30 12:38:31.000000000 -0400 @@ -0,0 +1,21 @@ +#ifndef __ASM_ARM_HARDWARE_ARM_TIMER_H +#define __ASM_ARM_HARDWARE_ARM_TIMER_H + +#define TIMER_LOAD 0x00 +#define TIMER_VALUE 0x04 +#define TIMER_CTRL 0x08 +#define TIMER_CTRL_ONESHOT (1 << 0) +#define TIMER_CTRL_32BIT (1 << 1) +#define TIMER_CTRL_DIV1 (0 << 2) +#define TIMER_CTRL_DIV16 (1 << 2) +#define TIMER_CTRL_DIV256 (2 << 2) +#define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable (versatile only) */ +#define TIMER_CTRL_PERIODIC (1 << 6) +#define TIMER_CTRL_ENABLE (1 << 7) + +#define TIMER_INTCLR 0x0c +#define TIMER_RIS 0x10 +#define TIMER_MIS 0x14 +#define TIMER_BGLOAD 0x18 + +#endif diff -uNr xen-unstable.hg/xen/include/asm-arm/arch-versatile/timex.h xen-arm-ver/xen/include/asm-arm/arch-versatile/timex.h --- xen-unstable.hg/xen/include/asm-arm/arch-versatile/timex.h 1969-12-31 19:00:00.000000000 -0500 +++ xen-arm-ver/xen/include/asm-arm/arch-versatile/timex.h 2008-11-14 11:42:05.000000000 -0500 @@ -0,0 +1,36 @@ +/* + * linux/include/asm-arm/imx/timex.h + * + * Copyright (C) 1999 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _ASM_ARCH_TIMEX_H_ +#define _ASM_ARCH_TIMEX_H_ + +#define ARCH_CLOCK_TICK_RATE 32000 + +extern u64 get_timebase(void); + +typedef u64 cycles_t; +static inline cycles_t get_cycles(void) +{ + cycles_t c; + c = get_timebase(); + return c; +} + +#endif diff -uNr xen-unstable.hg/xen/include/asm-arm/arch-versatile/uncompress.h xen-arm-ver/xen/include/asm-arm/arch-versatile/uncompress.h --- xen-unstable.hg/xen/include/asm-arm/arch-versatile/uncompress.h 1969-12-31 19:00:00.000000000 -0500 +++ xen-arm-ver/xen/include/asm-arm/arch-versatile/uncompress.h 2008-10-24 15:01:04.000000000 -0400 @@ -0,0 +1,46 @@ +/* + * arch/arm/mach-versatile/include/mach/uncompress.h + * + * Copyright (C) 2003 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#define AMBA_UART_DR (*(volatile unsigned char *)0x101F1000) +#define AMBA_UART_LCRH (*(volatile unsigned char *)0x101F102C) +#define AMBA_UART_CR (*(volatile unsigned char *)0x101F1030) +#define AMBA_UART_FR (*(volatile unsigned char *)0x101F1018) + +/* + * This does not append a newline + */ +static inline void putc(int c) +{ + while (AMBA_UART_FR & (1 << 5)) + barrier(); + + AMBA_UART_DR = c; +} + +static inline void flush(void) +{ + while (AMBA_UART_FR & (1 << 3)) + barrier(); +} + +/* + * nothing to do + */ +#define arch_decomp_setup() +#define arch_decomp_wdog() diff -uNr xen-unstable.hg/xen/include/asm-arm/arch-versatile/vic.h xen-arm-ver/xen/include/asm-arm/arch-versatile/vic.h --- xen-unstable.hg/xen/include/asm-arm/arch-versatile/vic.h 1969-12-31 19:00:00.000000000 -0500 +++ xen-arm-ver/xen/include/asm-arm/arch-versatile/vic.h 2008-10-27 11:59:55.000000000 -0400 @@ -0,0 +1,45 @@ +/* + * arch/arm/include/asm/hardware/vic.h + * + * Copyright (c) ARM Limited 2003. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARM_HARDWARE_VIC_H +#define __ASM_ARM_HARDWARE_VIC_H + +#define VIC_IRQ_STATUS 0x00 +#define VIC_FIQ_STATUS 0x04 +#define VIC_RAW_STATUS 0x08 +#define VIC_INT_SELECT 0x0c /* 1 = FIQ, 0 = IRQ */ +#define VIC_INT_ENABLE 0x10 /* 1 = enable, 0 = disable */ +#define VIC_INT_ENABLE_CLEAR 0x14 +#define VIC_INT_SOFT 0x18 +#define VIC_INT_SOFT_CLEAR 0x1c +#define VIC_PROTECT 0x20 +#define VIC_VECT_ADDR 0x30 +#define VIC_DEF_VECT_ADDR 0x34 + +#define VIC_VECT_ADDR0 0x100 /* 0 to 15 */ +#define VIC_VECT_CNTL0 0x200 /* 0 to 15 */ +#define VIC_ITCR 0x300 /* VIC test control register */ + +#define VIC_VECT_CNTL_ENABLE (1 << 5) + +#ifndef __ASSEMBLY__ +void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources); +#endif + +#endif diff -uNr xen-unstable.hg/xen/include/asm-arm/arch-versatile/vmalloc.h xen-arm-ver/xen/include/asm-arm/arch-versatile/vmalloc.h --- xen-unstable.hg/xen/include/asm-arm/arch-versatile/vmalloc.h 1969-12-31 19:00:00.000000000 -0500 +++ xen-arm-ver/xen/include/asm-arm/arch-versatile/vmalloc.h 2008-10-24 15:01:04.000000000 -0400 @@ -0,0 +1,21 @@ +/* + * arch/arm/mach-versatile/include/mach/vmalloc.h + * + * Copyright (C) 2003 ARM Limited + * Copyright (C) 2000 Russell King. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#define VMALLOC_END (PAGE_OFFSET + 0x18000000)